Nowadays, semiconductor fabrication industry is rapidly developing under guidance of Moore's law, performance and integration degree of an integrated circuit are constantly increased while power consumption of the integrated circuit is reduced as much as possible. Therefore, in future a subject of the semiconductor fabrication industry will focus on fabrication of an ultra-short channel device with high performance and low power consumption. After entering into a 22 nm technology node, a conventional planar field effect transistor has an increased leakage current, a more severe short-channel effect and a drain-induced barrier lowering (DIBL) effect so as not to be suitable for development of the semiconductor fabrication industry. In order to overcome the above problems, several new-structured semiconductor devices, such as a Double Gate FET, a FinFET, a Tri-Gate FET and a Gate-all-around (GAA) Nanowire (NW) FET have been proposed and have got a wide attention. By means of a multiple-gate structure, particularly a gate-all-around structure, a control ability of a gate to a channel can be greatly enhanced, so that it is difficult for an electric field to directly pass through the channel from a drain to a source. In this way, the drain-induced barrier lowering effect can be substantially reduced, the leakage current can be decreased, and the short-channel effect can be well suppressed. Since a good gate-control ability can be obtained by the gate structure, it is not necessary to perform a highly doping to the channel as in the conventional planar field effect transistor to suppress the short-channel effect. An advantage of lightly doping the channel is that a decrease of mobility due to scattering is reduced, so that the mobility in the multiple-gate structure device is greatly improved. Furthermore, because in a one-dimensional nanowire field effect transistor there is a one-dimensional quasi-ballistic transferring effect, the mobility of the device is further increased. Therefore, as a new-structured device, the GAA NE FET will become a promising option for replacing the conventional planar field effect transistor.
A silicon nanowire field effect transistor was formed through a synthesis method by Yi Cui et al. from Harvard University [Yi Cui, et al., Science 293, 1289 (2001)]. By using a high sensitivity of the silicon nanowire field effect transistor, a change of a PH value was successfully measured. However, several defects that are impossible to be overcome for such method for forming the silicon nanowire by synthesis lie in as follows. (1) Silicon nanowires grown by the synthesis do not have a uniform direction, in most of cases they are grown irregularly and have no uniform direction. (2) The silicon nanowires grown by the synthesis have various sizes and have a difficulty to be precisely controlled. (3) Such method, in which a bottom-up process method is used, is difficult to be compatible with a conventional semiconductor fabrication technology, in which a top-down process method is used.
Furthermore, a silicon nanowire field effect transistor was successfully fabricated over a bulk silicon substrate through using a SiGe sacrificial layer by Sun Dae Suk et al. from Samsung Electronics of Korea [Sung Dae Suk, et al., IEDM Tech. Dig., p. 717-720 2005.]. A core process used is to suspend the silicon nanowire by removing the SiGe sacrificial layer under a silicon film through wet etching. However, such fabrication process is complicated, and a fabrication cycle is long.
Also, a silicon nanowire field effect transistor was successfully fabricated over a SOI substrate by S. Bangsaruntip et al. from IBM [S. Bangsaruntip, et al., IEDM Tech. Dig., p. 297-300 2009]. A core process used by them is as follows. A pattern of a drain, a source and a fine bar connecting the drain and the source are formed on a slimmed silicon film formed by performing a slimming process for a silicon film over the SOI substrate, and a diameter of the silicon nanowire is reduced by subsequent hydrogen annealing process and sacrificial oxidation process, and a large turn-on current is then obtained by a lifting technology for the drain and the source.
Major defects of the above-described silicon nanowire fabrication method lie in as follows. (1) The cost of the SOI substrate is higher than that of the silicon substrate. (2) The lifting technology for the drain and the source is complicated.
As to problems in the above-mentioned methods for fabricating silicon nanowire field effect transistor, a method for fabricating a silicon nanowire field effect transistor based on wet etching is provided by an embodiment of the present invention. By using the method of the present invention, the silicon nanowire field effect transistor can be easily fabricated over a bulk silicon wafer. Furthermore, the entire process flow is completely compatible with a fabrication technology of a typical silicon-based ultra-large-scale integrated circuit. The fabrication process is simple and convenient, and has a short cycle. Also, a diameter of a silicon nanowire channel of the silicon nanowire field effect transistor fabricated by such process can be controlled to ten nm approximately. A gate-all-around structure can provide a superior gate-control ability, which is suitable for fabricating an ultra short channel device and is capable of further reducing a size of the device. Finally, the silicon nanowire field effect transistor fabricated by such method has small serial resistances between source and drain, so that a higher turn-on current can be obtained without performing an additional lifting technology for the source/drain.